Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal ...

As DRAM technologies scale to increasingly tighter pitches, the patterning requirements exceed the limits of conventional single-exposure DUV lithography. In advanced nodes such as D1b (1-beta), ...

(MENAFN- Asia Times) A Beijing-based state-owned enterprise reportedly has started research on a multiple-patterning process that can achieve the mass production of 5 nanometer chips. Naura Technology ...

Huawei Technologies Co and a confidential chipmaking partner in China have been advancing in semiconductor technology through patents for self-aligned quadruple patterning (SAQP), a method potentially ...

Nano-electronics research center imec and Nova Measuring Instruments (Nasdaq: NVMI), a leading innovator and key provider of metrology solutions for advanced process control used in semiconductor ...

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Self-aligned lithographic process techniques are playing an increasingly important role in advanced technology nodes. Even with the growing use of extreme ultraviolet (EUV) lithography, ...

(MENAFN- Asia Times) Huawei Technologies, a Shenzhen-based telecommunication equipment maker, is reportedly planning to make 3 nanometer chips with deep ultraviolet (DUV) lithography machines despite ...