EDN

Wafer Level Chip Size Package

This application note provides guidelines for the use of Wafer Level Chip Size Packages (WLCSP). The information in this application note can be used throughout the various stages of WLCSP use. This ...
Nasdaq

Akoustis Locks Process Flow for First Wafer-Level-Chip-Scale Package (WLCSP) for XBAW Filters

Charlotte, N.C., Feb. 01, 2021 (GLOBE NEWSWIRE) -- Akoustis Technologies, Inc. (NASDAQ: AKTS) (“Akoustis” or the “Company”), an integrated device manufacturer (IDM) of patented bulk acoustic wave (BAW ...
EDN

Polymer slims wafer-level chip-scale packages

PORTLAND, Ore. — Tessera Technologies Inc. (San Jose, Calif.) announced today (Dec. 11) what it says is one of the slimmest surface-mountable wafer-level chip-scale packages (WLCSPs) available for ...
Electronic Design

Wafer-Level Chip-Scale Package Favors Small-Form-Factor ASICs

A fully qualified, high-performance, low-power and small-form-factor wafer-level chip-scale package (W-CSP) developed by Oki Semiconductor satisfies a wide range of ASIC design demands. Targeting chip ...
Semiconductor Engineering

Fan-Out Wafer Level eWLB Technology As An Advanced System-In-Package Solution

System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and ...
Electronic Design

Microchip Expands UNI/O EEPROM Line With Wafer-Level Chip-Scale And TO-92 Packages

Microchip has developed a single-I/O bus UNI/O EEPROM devices in miniature, wafer-level chip-scale and TO-92 packages, in addition to the 3-pin SOT-23 package. Measuring 0.85 mm x 1.38 mm, the ...
Digi Times

STATS ChipPAC fan-out wafer-level packaging shipments exceed 1 billion units

STATS ChipPAC has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded wafer-level ball grid array (eWLB), according to the company. Save my User ID ...
Nasdaq

Aehr Announces Shipment of Initial FOX-XP Wafer-Level Burn-In System for Advanced AI Processors

FREMONT, CA / ACCESS Newswire / February 28, 2025 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has completed shipment of its ...
Semiconductor Engineering

Easing The Stress For Package-Level Burn-In

Considered something of a necessary evil, burn-in of IC packages during production does a great job of weeding out latent defects so they don’t turn into failures in the field. But as AI and ...
Digi Times

South Korea initiates major R&D project to boost chips packaging competitiveness

Recognizing the strategic importance of semiconductor packaging technology, the South Korean government is reportedly initiating a major packaging technology R&D project aimed at assisting companies ...
Joplin Globe

Aehr Seeing Momentum in Package-Level Burn-In Alongside Expanding Wafer-Level Burn-in Demand

FREMONT, CA / ACCESS Newswire / November 12, 2025 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in solutions, today announced the shipment of its Dual-Echo™ ...
Business Wire

OmniVision’s New Medical Wafer-Level Camera Module Improves Image Quality for Single-Use Endoscopy in Smallest Parts of Anatomy

SANTA CLARA, Calif.--(BUSINESS WIRE)--OmniVision Technologies, Inc., a leading developer of advanced digital imaging solutions, today announced the OVMed® OCHTA camera module with quadruple the ...