TechRepublic

8 Bit RISC Processor Using Verilog HDL

RISC is a design philosophy to reduce the complexity of instruction set that in turn reduces the amount of space, cycle time, cost and other parameters taken into account during the implementation of ...
TechRepublic

64-Bit RISC Processor Design Using Verilog

The Reduced Instruction Set Computer (RISC) is a microprocessor design principle that favors a smaller and simpler set of instructions that all take same amount of time to execute. RISC architecture ...
Hackaday

RISC-V: Why The ISA Battles Aren’t Over Yet

A computer processor uses a so-called Instruction Set Architecture to talk with the world outside of its own circuitry. This ISA consists of a number of instructions, which essentially define the ...
Design-Reuse

Brand new 32-bit RISC core: XAP3 ASIC processor liberates embedded systems industry with very high code density, low power and software flexibility

September 14, 2004 - Today, Cambridge Consultants launches a novel 32-bit RISC core that brings a new level of code density and power economy to deeply-embedded applications. The XAP3 core is ...
Design-Reuse

A formal-based approach for efficient RISC-V processor verification

The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also ...
Liliputing

Open source XiangShan RISC-V processor could eventually challenge ARM Cotex-A76

At this year’s RISC-V World Conference China, a team of more than two dozen students and professors from the Chinese Academy of Science (CAS) have unveiled the XiangShan processor that promises big ...