EDN

Generate FPGA designs from M-code

DSP systems are best described by using a combination of both graphical-and language-based methods. The MathWorks, an industry leader in DSP modeling software, caters to this dichotomy by providing a ...
EDN

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
Electronics Weekly

FPGA toolkit has IEEE754 floating point libraries

Celoxica has available a toolkit for floating-point arithmetic implementation in high-density programmable logic. The IEEE 754 compliant libraries support single, double and custom precision ...
Electronic Design

An Easier Path To RTL For DSP Algorithms

Why are so many designers turning to FPGA implementation for DSP designs? Considering the price/performance ratio for today's high-end FPGAs, not to mention the large numbers of DSP blocks and ...
Design-Reuse

How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs

Here we provide rational for using Centar’s floating-point IP core for the new Altera Arria 10 and Stratix 10 FPGA platforms. After a short contextual discussion section, a comparison of various FFT ...
Electronic Design

PCs Bridge The Gap Between DSP And FPGA Designers

Typically, DSP designers are unfamiliar with FPGA design tools, and FPGA designers are unfamiliar with DSP algorithms. But when Sandia National Laboratories needed to replace an analog implementation ...