EDN

Building high-speed FPGA memory interfaces

Building reliable, high-speed memory interfaces target FPGA I/O structures as well as intellectual property (IP) used within design software to allow rapid configuration of memory interfaces. These ...
EDN

Optimizing Up/Down Conversion with FPGA Techniques

Digital upconverters (DUCs) and digital downconverters (DDCs) are important components of every modern wireless base station design. While many DUC and DDC designs are available, there is a clear call ...
Design-Reuse

DDR SDRAM Controller IP Designed for Reuse

This paper deals with reusability issues in the development of a double data rate (DDR) SDRAM controller module for FPGA-based systems. The development of integrated systems-on-a-chip (SoC) is based ...
Design-Reuse

Optimizing Up/Down Conversion with FPGA Techniques

Digital upconverters (DUCs) and digital downconverters (DDCs) are important components of every modern wireless base station design. While many DUC and DDC designs are available, there is a clear call ...