Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, ...

Structured ASICs require developers to re-program only the top level metal layers when customizing their designs, enabling faster development time and low unit cost. However, many structured ASICs ...

Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought ...

I'm fast approaching the one year mark with my current employer since I graduated last year. Previously, I did three four month work terms with them and they were for the most part interesting. I took ...

Santa Cruz, Calif. — Claiming a breakthrough in ASIC debugging, Synplicity Inc. this week will release details about TotalRecall, which it says will bring full debug visibility to FPGA prototypes used ...

The Certify 5.0 verification synthesis software has been launched for FPGA-based ASIC prototypes. The new version can perform partitioning, gated-clock conversion, andpin-multiplexing automatically.

1. In a big company, doing ASIC design verification for a WCDMA modem for 3G cellular chips. 2. Small company, doing Embedded Software Programming. Working on the design and implementation of layer 1 ...

In a move described as a 'significant enhancement' to its product range, MathWorks has launched HDL Coder, which allows HDL code to be generated directly from MATLAB and used to implement fpgas and ...

As technology continues to evolve, the need for semiconductor chips also increases. The semiconductor industry lies underneath much of the technological progress, powering devices and systems that ...

Online identification specialist, Veritas, has partnered with AerVision Technologies to automate the verification process for airline crew when they arrive at Australian airports. Technology Companies ...