Designed the 16-bit pipelined serial/parallel multiplier by utilizing the MOSIS (TSMC) 0.35 μm CMOS process. The 16-bit Pipelined Serial/Parallel Multiplier is capable of multiplying two 16-bit ...
Consisting of three IC families that span a broad range of applications, the dsPIC series of digital signal processors (DSPs) integrates on-chip a fully-implemented digital signal processor engine and ...
Fabless silicon intellectual-property vendor Ceva Inc. (San Jose, Calif.) has introduced the Ceva-TeakLite-III family of digital signal-processing cores, targeting 2.5G and third-generation cellular ...
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